The Government of India’s DIR-V program aims to establish India as a leader in electronics. As part of the DIR-V program, C-DAC has successfully completed the design and development of the VEGA series of microprocessors, including India’s first indigenous 64-bit multi-core RISC-V-based superscalar out-of-order processor. The VEGA series comprises 32/64-bit single, dual, and quad-core superscalar out-of-order high-performance processor cores based on the RISC-V instruction set architecture.
One VEGA-based System-on-Chip (SoC) ASIC and two DIR-V VEGA processor-based development boards were launched during the visit of Shri Ashwini Vaishnaw, the Honourable Minister of Railways, Minister of Information and Broadcasting, and Minister of Electronics and Information Technology, in the gracious presence of Shri S. Krishnan, Secretary of the Ministry of Electronics and Information Technology (MeitY); Smt. Sunita Verma, Group Coordinator (R&D), MeitY; Shri E. Magesh, Director General; Shri Sanjay Wandhekar, Centre Head Pune; and other senior officials.
Single-Core VEGA Processor Based THEJAS64 SoC ASIC in SCL 180nm
C-DAC announces the successful fabrication of THEJAS64, a 64-bit single-core SoC chip at SCL, Chandigarh. This landmark achievement marks India’s advancement in microprocessor technology, which is fully based on indigenous design and fabrication using the open-standard RISC-V architecture. It is suitable for diverse applications, ranging from embedded systems to industrial use cases, thereby enhancing India’s technological independence and fostering a robust and secure domestic ecosystem.
ARIES NOVA & ECO Development Boards
C-DAC announces the launch of the ARIES NOVA and ECO development boards, a new hardware platform for embedded systems development, powered by the indigenous THEJAS32 SoC featuring the VEGA ET1031 microprocessor. ARIES NOVA is a compact and breadboard-friendly design, ideal for IoT and wearable applications, affordable robotics, and interactive projects that require a small, easy-to-use microcontroller. ARIES ECO is a cost-effective development board for embedded systems enthusiasts. Its versatile features, including multiple communication interfaces and GPIOs, are added advantages that support standalone operation with various power options. This cost-effective platform is expected to be a favorite among budding talents in the embedded arena.
The open-source RISC-V architecture enables flexibility and innovation and fosters hands-on learning and development in embedded systems.
The launch of the VEGA development boards and indigenous processors by Shri Ashwini Vaishnaw, the Honourable Minister of Railways, Minister of Information and Broadcasting, and Minister of Electronics and Information Technology, gives India significant impetus in the progress of a secure technological ecosystem. This reflects the spirit of Atmanirbhar Bharat, reducing reliance on imported technology.
Shri S. Krishnan, Secretary of the Ministry of Electronics and Information Technology, motivated the teams at C-DAC and urged them to anchor such opportunities in futuristic developments. He mentioned that as an applied R&D lab, C-DAC can act as a catalyst in transforming many of the R&D outcomes into usable solutions across industries.
Shri E. Magesh, Director General, noted that C-DAC’s three-decade leadership has transformed India’s technological landscape. Central to this domain, we have played a pivotal role in the evolution of the DIR-V program over the past decade, contributing to today’s reality through sustained efforts.
Smt. Sunita Verma, Group Coordinator (R&D), MeitY, lauded the efforts in rapid technological progress and appreciated C-DAC for playing a vital role in driving innovation and creating groundbreaking technologies.
